Design of Multi Bit Flip Flop in FIR Application Using Clustering Algorithm

In Integrated Circuit industry power has become a major contribution. The main attribute is the clock power in circuits of VLSI. In today’s VLSI design scenario, power utilization by clocking takes up a vital role especially in design that uses deeply scaled CMOS technology. Proficient power utilization tends to be an important constraint in modern IC design. The underneath idea of multi bit flip flop is to reduce the inverter number by sharing among flip flop. Indulging multi bit flip flop in synchronous design is becoming a considerable method for reducing clock power. The single bit flip flop cells uses a mutual number of inverter that possess high driving capability to drive over clock signal. Grouping of such cells to form multi bi flip flop can spare drive strength, dynamic power and area of common inverter where there is no compromise among the necessary constraint among area and power. In this paper, a Hausdorff clustering algorithm is utilized to obtain nearest clustering for merging flip flops. The multi bit technique is introduced in FIR circuit to lessen power as well as area. This satisfies with the above given constraints. According to the experimental results, our algorithm significantly reduces clock power by 25.8% and it is found that total gate count is reduced from 186 to 128. The delay is curtailed upto 1.19 ns which increases the speed. KeywordsClock Power, Cluster, Delay, Manhattan Distance, Merging, Multi Bit Flip Flop